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Freescale Semiconductor /MKV56F24 /SystemControl /ID_ISAR2

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Interpret as ID_ISAR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)LOADSTORE_INSTRS 0 (00)MEMHINT_INSTRS 0 (00)MULTIACCESSINT_INSTRS 0 (00)MULT_INSTRS 0 (00)MULTS_INSTRS 0 (00)MULTU_INSTRS 0 (00)REVERSAL_INSTRS

REVERSAL_INSTRS=00, MULT_INSTRS=00, MULTIACCESSINT_INSTRS=00, MULTU_INSTRS=00, LOADSTORE_INSTRS=0, MULTS_INSTRS=00, MEMHINT_INSTRS=00

Description

Instruction Set Attributes Register 2

Fields

LOADSTORE_INSTRS

Indicates the supported additional load and store instructions

0 (0): None supported, ARMv7-M reserved

1 (1): Adds support for the LDRD and STRD instructions
MEMHINT_INSTRS

Indicates the supported Memory Hint instructions

0 (00): None supported, ARMv7-M reserved.

1 (01): Adds support for the PLD instruction, ARMv7-M reserved.

2 (10): As for 1, ARMv7-M reserved.

3 (11): As for 1 or 2, and adds support for the PLI instruction.
MULTIACCESSINT_INSTRS

Indicates the support for multi-access interruptible instructions

0 (00): None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M reserved.

1 (01): LDM and STM instructions are restartable.

2 (10): LDM and STM instructions are continuable.
MULT_INSTRS

Indicates the supported additional Multiply instructions

0 (00): None supported. This means only MUL is supported. ARMv7-M reserved.

1 (01): Adds support for the MLA instruction, ARMv7-M reserved.

2 (10): As for 1, and adds support for the MLS instruction.
MULTS_INSTRS

Indicates the supported advanced signed Multiply instructions

0 (00): None supported, ARMv7-M reserved

1 (01): Adds support for the SMULL and SMLAL instructions

2 (10): As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions.

3 (11): As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions.
MULTU_INSTRS

Indicates the supported advanced unsigned Multiply instructions

0 (00): None supported, ARMv7-M reserved

1 (01): Adds support for the UMULL and UMLAL instructions.

2 (10): As for 1, and adds support for the UMAAL instruction.
REVERSAL_INSTRS

Indicates the supported Reversal instructions

0 (00): None supported, ARMv7-M reserved

1 (01): Adds support for the REV, REV16, and REVSH instructions, ARMv7-M reserved.

2 (10): As for 1, and adds support for the RBIT instruction.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data